With help of hardware transactional memory multiple logical processors execute
a critical region speculatively, e.g. without explicit synchronization.
If the transactional execution completes successfully, then all memory operations performed within the transactional region are commited without any inter-thread serialization.
When the optimistic execution fails, the processor aborts the transaction and discards all performed modifications.
In non-transactional code a single lock serializes the access to a critical region. With a transactional memory, multiple logical processor start a transaction and update the memory (the data) inside the ciritical region. Unless some logical processors try to update the same data, the transactions would always succeed.
TSX is Intel's implementation of hardware transactional memory in modern Intel
In TSX the hardware keeps track of which cachelines have been read from and which have been written to in a transaction. The cache-line size (64-byte) and the n-way set associative cache determine the maximum size of memory in a transaction. For instance if a transaction modifies 9 cache-lines at a processor with a 8-way set associative cache, the transaction will always be aborted.
TXS is enabled if property
A TSX-transaction will be aborted if the floating point state is modified inside a critical region. As a consequence floating point operations, e.g. store/load of floating point related registers during a fiber (context) switch are disabled.
TSX can not be used together with MSVC at this time!
Boost.Fiber uses TSX-enabled spinlocks to protect critical regions (see section Tuning).